On 21/04/2011 12:56, Olin Lathrop wrote: > V G wrote: >> > I learn best by examples. > Now we're getting at the root of the problem. > > Complex things can't be learned by example. You may think you learn best= by > example, but that's only your desire for instant gratification getting in > the way. > > Grow up and get over it. Sit down, and read the docs. It may take a cou= ple > of days before you touch anything else. This is something where you have= to > truly*understand* what's going on and have the options in the back of yo= ur > mind at every step. Monkey-see monkey-do examples won't show you all the > choices that were made or what else could have been done. I'd not word it the same, but I 100% agree with the point that is being made. FPGA is really HW design. Like acres of 74xx series chips. But using a=20 specification language rather than schematics to document the design. In fact if it's simple, or you are mad, or you very very expert with the=20 FPGA architecture and HW design, you CAN enter the FPGA specification as=20 a "real" schematic. You can view an "equivalent" schematic of any VHDL=20 or Verilog specification with the Xilinx tools. Use slow original 74 series or 4000 series or else a good simulator, so=20 you can "see" the issues. The Hardware Description/Specification Languages look deceptively=20 simple, especially Verilog for a C programmer. In fact if you have not done HW logic recently or at all, bread board=20 some 74xNN type designs with a) Asynchronous logic, such as D-type ripple counter with 4 stages (/2,=20 /4 /8 /16) b) Synchronous logic, maybe start with a JK counter with a single clock=20 to all flip flops. (synchronous /2, /4 /8/16) Connect 4 input NAND to four stages of each of above designs to detect=20 "all 1s". (a) and (b) give quite different results. put an inverter on the nand gate and compare the primary clock=20 transitions with edges on the output of inverter. Feed both signals to a=20 2 i/p nand driving a D-type flip flop. Are D-Types "always" bad? Take 3 x D-Type flip flops: Drive a D-Type as /2 and drive a pair, one from Q and one from !Q=20 outputs both as /2 ( Clock goes to clock, D connects to !Q) Now compare Q2 and Q3 outputs. Having done all these on a Logic Simulator or real breadboard with a=20 Logic analyser, now do these designs in VHDL and Verilog. The Xilinx tools includes a logic simulator/tester. You can feed the=20 clock and see the output waveforms as per the 4000/7400 series=20 breadboard or simulation, all without download to FPGA. Finally download each to FPGA using Pin Definition tool to define the=20 input pin and all the output pins for the logic analyser. If you want you can in both the real logic bread board connect LEDs to=20 all the Q and !Q pins (via buffer such as ULN2003 etc) and use 1Hz clock=20 (you want Logic Analyser and 1MHz clock for 4000 series, 10MHz 7400=20 series and 100MHz on FPGA to see the issue with example (a) and verify=20 the the results). These are very trivial examples, but illustrate a few of points. 1) Synchronous vs async random logic issues 2) Race conditions 3) Sometimes asynchronous logic is fine. 4) Ultimately verilog and VHDL are not programming languages, but an=20 alternate to schematics to specify hardware. The idea is to hide the=20 actual implementation such that the same design should usually work on=20 different FPGAs and even on ASIC, providing you are understanding what=20 you do. Of course if doing DSP, knowing how much RAM (for samples, coefficients,=20 taps) and how many "real" HW multiplier / accumulators exist is=20 important to know. But this is in same sense that you can design a logic=20 circuit and it might not work at all on 4000 series logic or 74HC logic=20 but needs a faster family, or the design might work on ANY logic family=20 as it's less than 1MHz. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .