On Apr 21, 2011, at 3:45 AM, Michael Watterson <mike@radioway.org> wrote:

> On 21/04/2011 08:21, V G wrote:
>> I totally understand that this is not a CPU. I already started doing Ver=
ilog
>> now. Got some neat stuff running on the board, that I've written myself.=
 It
>> would be counterproductive to switch to VHDL now.
>=20
> You only think that. A week of VHDL would really help your verilog.
>=20

I would agree. If you plan on doing verilog be sure to read some of mr. Cum=
mings papers. There is one that goes through some of the common gotchas ( v=
erilog has some nice ones!)

http://www.sunburst-design.com/papers/

MD
--=20
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