I agree, VHDL is rather mind-bending and not in a good way.  I finally=20
got "FPGA prototyping by VHDL examples" by Pong P. Chu and it helped get=20
me to done for a project.

I suggest verilog as well.

J


Philip Pemberton wrote:
> On 17/04/11 16:08, V G wrote:
>> Which one should I start learning? Verilog or VHDL? Also, what's up with
>> this SystemVerilog superset?
>
> Verilog.
>
> If you've ever used C, you'll find it much easier to get your head
> around the block structures and expressions. I think the operator
> precedence rules might be slightly different, but generally it'll do as
> you expect.
>
> VHDL will drive you to insanity, and then some...
>
--=20
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