On Fri, 8 Apr 2011 07:44:27 -0400, you wrote: >On Fri, Apr 8, 2011 at 6:23 AM, Mike Harrison wrote= : > >> A few - onboard memory will probably be the first limit you hit >> > >Thanks. I'll look for memory upgrade options. > >As above, memory may be more of an issue than gate. Also for complex desig= ns >> teh compile process >> will be quicker for a larger device as it doesn't have to try so hard to >> fit it. >> > >Is compile time *actually* an issue? I mean, to compile a C program in C32= , >it takes less than a second or so. How long would it take to compile an FP= GA >program when the compiler is trying hard to fit it? How long does it take = on >average? Compiling a FPGA is many orders of magnitude more work than compiling code.= =20 A vague analogy is compiling a description of a circuit board containing te= ns of thousands of parts into a finished PCB layout.=20 It has to not only parse your code into logic, it then has to place and rou= te it on the FPGA's resources, and do timing analysis, then often rip-up and repeat the process= as necessary until it meets timing requirements, which means the time can increase exponentially = as the device approaches capacity. 30 secs would be a typical bare-minimum compile time for a trivial design o= n a fast PC, due to the number of different tools that are needed for the whole process. Hours or e= ven days are not uncommon for high-end stuff on a fairly full device.=20 >> Several thousand $ each., >> For example : >> >> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=3DXC6VL= X760-L1FFG1760I-ND >> > >Whoah. Why? As in, what features/performance/whatever do you get for a $20 >000 chip? A massive piece of silicon with an awful lof of gates and pins.... --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .