'William Chops" Westfield ' Core details, sort of. Perhaps I'm looking for the non-core details. > For example, the PRM describes "up to 8 non-maskable traps", That's a core detail. "Core" means the basic CPU core. That's the part that is invariant accross different models. The stuff that changes between models is the peripheral mix, the amount of RAM and ROM, and I/O pins. The hardware that crunches thru the instruction set is the same or very nearly the same for 24F, 24H, 30F, and 33F. The main difference is that the 30F and 33F have DSP capabilities added to the core. The newer ones also have DMA capability, although you could probably argue either way whether that's a peripheral addon or a extension of the core. > but individual chips seem to implement only a subset of that > number. Are all 8 types of trap "defined" (but not all implemented > on some chips), or is 8 a convenient power of two that they haven't > decided how to fully utilize yet? Traps are described in great detail in the family reference manual. For example, look at Section 6 of the 33F Family Reference Manual. It shows th= e original 4 possible traps plus the new DMA error trap. The remaining 3 possible traps are "reserved", meaning they could be implemented in the future. They will likely be used in connection with features added to the core in future products. ******************************************************************** Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products (978) 742-9014. Gold level PIC consultants since 2000. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .