One small change might fix it:

The two most relevant are AR
(address ready) and DR (data ready). The master puts an address on the
bus, then sets AR high. The slave sees AR high, drops DR, puts the
requested data on the bus, and sets DR high. The master then reads the
data, drops AR, puts a new address on the bus, and then sets AR high
again.

to:

The two most relevant are AR (address ready) and DR (data ready). The maste=
r puts an address on the bus, then sets AR high. The slave sees AR high, pu=
ts the
requested data on the bus, drops DR. The master then reads the data, drops =
AR. The slave sees AR low, and sets DR high. The master sees DR high, puts =
a new address on the bus, and then sets AR high again.

Kerry




Josh Koffman wrote:
> What I've actually got is 4 control lines, though some aren't really
> connected directly to the data transfer. The two most relevant are AR
> (address ready) and DR (data ready). The master puts an address on the
> bus, then sets AR high. The slave sees AR high, drops DR, puts the
> requested data on the bus, and sets DR high. The master then reads the
> data, drops AR, puts a new address on the bus, and then sets AR high
> again.
>
> I had my logic analyzer on it last night, and while I'm not near it
> now, I'm nearly certain that the last thing I was seeing prior to the
> stall was the slave drop, then reassert DR, but no response from the
> master. When I halted the master the INT2 flag wasn't set. I'm going
> to re-check that as soon as I can.
>
> Josh
>  =20



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