How does the slave know when the master has read the data? Is it=20 possible that the slave is sending data, and then sending the next data=20 before the master gets around to reading the first data? I usually use 2 control lines, Master to Slave and Slave to Master. =20 Lets call them MS and SM. When the slave wants to send data, it sets SM=20 high. When the Master see SM high, it reads the data and sets MS high. =20 When the slave sees MS high, it sets SM low. When the master sees SM=20 low, it lowers MS. When the slave sees MS low, it knows it can send the=20 next set of data. This works 100% of the time, with no chance of missed=20 data. Kerry Josh Koffman wrote: > Hi all. > > I'm seeing some weird behaviour with the external interrupts, and I'm > not sure what's going on. I'm using an 18F4321. This chip is > exchanging data with another 18F4321 over a parallel bus (not the PSP, > something I've worked up with a few control pins). I am using INT2 as > an indicator that the slave chip has dropped the data ready (DR) line, > put new data on the bus, and then reasserted DR. Because some other > things are a bit more timing sensitive, I am polling for the INT2 flag > in my mainline. I've basically moved as much as I can out of the ISR > to help ensure a consistent response to the INT0 interrupt (more on > that below). Everything works great...well, sort of. > > On INT0 I have a sensor that is producing and interrupt about every > 1/12s (0.083s). Once I connect up the sensor, I find that INT2 doesn't > consistently set the flag anymore. The sensor is dealt with in the ISR > and triggers a burst of data out the UART. Instead of polling, I've > tried dealing with it in the ISR. I've tried both edge settings > (trigger on transition low and trigger on transition high). I've > checked the code and I can't see any unintentional clearings of the > flag. Because it doesn't flag the change in the control signal, my > data exchange stalls. > > I'm really confused by this one. I can't think of a reason why INT2 > isn't catching the transitions. Is there something I'm just missing > here? > > Thanks! > > Josh > =20 --=20 Internal Virus Database is out-of-date. Checked by AVG Anti-Virus. Version: 7.0.289 / Virus Database: 267.11.13 - Release Date: 10/6/05 --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .