Hi all.

I'm seeing some weird behaviour with the external interrupts, and I'm
not sure what's going on. I'm using an 18F4321. This chip is
exchanging data with another 18F4321 over a parallel bus (not the PSP,
something I've worked up with a few control pins). I am using INT2 as
an indicator that the slave chip has dropped the data ready (DR) line,
put new data on the bus, and then reasserted DR. Because some other
things are a bit more timing sensitive, I am polling for the INT2 flag
in my mainline. I've basically moved as much as I can out of the ISR
to help ensure a consistent response to the INT0 interrupt (more on
that below). Everything works great...well, sort of.

On INT0 I have a sensor that is producing and interrupt about every
1/12s (0.083s). Once I connect up the sensor, I find that INT2 doesn't
consistently set the flag anymore. The sensor is dealt with in the ISR
and triggers a burst of data out the UART. Instead of polling, I've
tried dealing with it in the ISR. I've tried both edge settings
(trigger on transition low and trigger on transition high).  I've
checked the code and I can't see any unintentional clearings of the
flag. Because it doesn't flag the change in the control signal, my
data exchange stalls.

I'm really confused by this one. I can't think of a reason why INT2
isn't catching the transitions. Is there something I'm just missing
here?

Thanks!

Josh
--=20
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
=A0 =A0 =A0 =A0 -Douglas Adams

--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.