Olin Lathrop wrote:
> Hmm.  I tried it a few times and was not impressed.  It seemed to find
> trivial things that weren't errors at all.  You think you've submitted a
> board to Advanced Circuits and go home.  Then you find out that Free DFM
> kicked out some stuff which aren't errors, but which hold up your board
> anyway.  One more day lost.
>
> Free DFM also checks against the Advanced Circuit desing rules, which may
> not be the rules you want to design against.  For example, I like to stic=
k
> to 8mil width and space unless there is a good reason not to.  Every boar=
d
> house I've run accross can do at least that, most can do better.  I think
> Gold Phoenix specifies 7/7 mil for their low cost prototype service.  The=
y
> can do better, but charge extra.  AC probably has more relaxed rules from
> the start.  So a board that Free DFM says is OK may not be OK for the Gol=
d
> Phoenix low cost prototype service.
>
> Checking the board is what the Eagle DRC is for.  On every design you sho=
uld
> run ERC when done with the schematic, then DRC before releasing the board=
..
> I actually run DRC several times on a board, particularly after I've done
> some manual routing and I want to make sure I didn't violate spacing
> somewhere.
>
>   =20
I like FreeDFM to catch gross errors, like flipped layers (which is a=20
concern based on the original post).  It does complain about minor=20
things at times.

A shortcoming of Eagle's DRC is that it doesn't check the final output -=20
the Gerber files.  The design can be perfect but errors introduced at=20
the final step.  When I installed a new version of Eagle, the CAM=20
processor default was for mirrored bottom layers.  With all the options,=20
it's easy to overlook especially since previous versions hadn't=20
defaulted that way.  FreeDFM caught that error for me which could have=20
been a costly mistake otherwise.

Jon



--=20
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