On Sat, 2011-03-05 at 19:28 +0000, Philip Pemberton wrote:
> On 05/03/11 17:02, Herbert Graf wrote:
> > That said, FPGAs have INCREDIBLE internal clock generation capabilities=
..
> > Most have numerous PLLs and clock dividing logic. Many have clock delay
> > blocks as well. Feed an FPGA one clock and your design can use dozens i=
f
> > need be.
>=20
> Although in synchronous designs (which is what FPGAs are really good=20
> for) it's frowned upon to use logic to generate a clock. That is, to=20
> have a clock driving (e.g.) a counter, then output a clock based on the=20
> value of that counter. The changing values can cause issues with glitches=
..

You are absolutely correct, but to be clear to others, I wasn't talking
about using "the fabric".

Most FPGAs have dedicated clocking logic used to bump up or down a clock
speed, along with supplying phased clocks, and even deskewing blocks to
eliminate the input propagation delay from clock pin to logic.

I think the point both of us are making is clocking in an FPGA is
something you have to be VERY careful about, since one line of code can
have a tremendous impact on whether your design will ever function
consistently.

TTYL

--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.