On Sat, Mar 5, 2011 at 2:28 PM, Philip Pemberton <piclist@philpem.me.uk> wr=
ote:
> Although in synchronous designs (which is what FPGAs are really good
> for) it's frowned upon to use logic to generate a clock. That is, to
> have a clock driving (e.g.) a counter, then output a clock based on the
> value of that counter. The changing values can cause issues with glitches=
..
>

I believe the term typically used for this is "gated clock."

--=20
Martin K.
--=20
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