On 05/03/11 17:02, Herbert Graf wrote:
> That said, FPGAs have INCREDIBLE internal clock generation capabilities.
> Most have numerous PLLs and clock dividing logic. Many have clock delay
> blocks as well. Feed an FPGA one clock and your design can use dozens if
> need be.

Although in synchronous designs (which is what FPGAs are really good=20
for) it's frowned upon to use logic to generate a clock. That is, to=20
have a clock driving (e.g.) a counter, then output a clock based on the=20
value of that counter. The changing values can cause issues with glitches.

As a bonus you also get clock skew -- 1*Tpd for each gate the clock=20
passes through. So if you do too much division of a single clock, you=20
get setup and hold time violations. These nasty little critters can,=20
will and often do make designs go metastable -- "it worked five minutes=20
ago, but it doesn't work now". Or there's the even more insidious "It=20
works on that board, but not this one..!"

The more generally accepted way to do it is to have a single master=20
clock, and use division logic to generate clock enable signals. The=20
clocked circuitry essentially ANDs the clock and CKE at the terminus.=20
Your clock signal goes along one of the low-latency clock routes inside=20
the FPGA, while the CKE goes through the logic fabric. This helps to=20
reduce the risk of a sample/hold violation.

FPGA design is fun.

--=20
Phil.
piclist@philpem.me.uk
http://www.philpem.me.uk/
--=20
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