On Sat, 2011-03-05 at 05:16 -0500, V G wrote:
> Thanks for the detailed reply, Oli.
>=20
> 1. To start off with basic things (hobby use, but with potential to do cr=
azy
> things like reading at 400M samples/s), which would you recommend,  PAL,
> CPLD, or FPGA?

Start with FPGAs.

> 2. How is "speed" actually rated for these types of devices? Clock speed?=
 If
> so, what is the clock speed generally around? Without even thinking, I wo=
uld
> assume reading at 400M samples/s would require at least 400 MHz. Do these
> things use crystals as a clock source?

Clocking in an FPGA is a whole other story.

There is no "one" clock in an FPGA, you can define pretty much as many
clocks as you require (up to the clock network routing in the particular
FPGA you use).

As for source, that depends. Most FPGAs don't have crystal drivers, so
you need to supply either a canned oscillator or other clock source (say
a clock chip).

That said, FPGAs have INCREDIBLE internal clock generation capabilities.
Most have numerous PLLs and clock dividing logic. Many have clock delay
blocks as well. Feed an FPGA one clock and your design can use dozens if
need be.

One design I did had about 10 different clocks, ranging from ~300kHz, to
80MHz, to 148.5MHz.

TTYL

--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.