Oli Glaser wrote:

> On 05/03/2011 10:16, V G wrote:
>> 2. How is "speed" actually rated for these types of devices? Clock
>> speed? If so, what is the clock speed generally around? Without even
>> thinking, I would assume reading at 400M samples/s would require at
>> least 400 MHz. Do these things use crystals as a clock source?
>=20
> Speed is difficult as it depends what you do with them - the ratings
> are roughly for the fastest switching the gates are capable of,
> though this will drop quickly as complexity increases. For example
> you might have a 350MHz FPGA - an 8 bit counter might run at 300MHz
> on there, but a processor core (8051 etc) might only run at 50MHz.
> Often the datasheets will give rough guides of what speeds various
> things will run at. The clock will usually be driven by a lower speed
> crystal oscillator into a PLL/DLL on the FPGA to generate the high
> speed clock. Or if you want you can drive the FPGA directly from the
> crystal at a lower speed.

In certain applications, you don't even use a clock like in a
synchronous device like a microcontroller. While they all have some sort
of clock line that feeds the cells, they can work independently of the
system clock -- just like any other logic. This is especially common
when using e.g. CPLDs as glue logic.=20

The speed is basically limited by the maximum clock speed (for
clock-based designs) and the propagation delays. Which, as Oli says,
depends on the complexity of a given design, because the more gates and
flip-flops you put in series in a signal path, the slower it becomes, as
the delays add up for each element.

Basically, while you program these, it's more like hardware design than
writing a program for a micro. If you look at a manual for one of these,
you'll see how the internal structure is and everything that has been
said will become clearer.

Gerhard
--=20
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