On 05/03/2011 10:16, V G wrote:
> 1. To start off with basic things (hobby use, but with potential to do cr=
azy
> things like reading at 400M samples/s), which would you recommend,  PAL,
> CPLD, or FPGA?

PAL is a general term for CPLDs, FPGAs etc..
To start off with the basic stuff, I would go for a small FPGA or CPLD.=20
However you can do a simple design on any of them as it's up to you how=20
many gates you use - for instance you could use a 1M gate FPGA and just=20
implement a simple counter/adder or something (it would be a very=20
expensive counter though :-)  )
I started with FPGAs as you can probably do the most with them, though=20
CPLDs have their uses/advantages too.


> 2. How is "speed" actually rated for these types of devices? Clock speed?=
 If
> so, what is the clock speed generally around? Without even thinking, I wo=
uld
> assume reading at 400M samples/s would require at least 400 MHz. Do these
> things use crystals as a clock source?

Speed is difficult as it depends what you do with them - the ratings are=20
roughly for the fastest switching the gates are capable of, though this=20
will drop quickly as complexity increases. For example you might have a=20
350MHz FPGA - an 8 bit counter might run at 300MHz on there, but a=20
processor core (8051 etc) might only run at 50MHz. Often the datasheets=20
will give rough guides of what speeds various things will run at.
The clock will usually be driven by a lower speed crystal oscillator=20
into a PLL/DLL on the FPGA to generate the high speed clock. Or if you=20
want you can drive the FPGA directly from the crystal at a lower speed.


--=20
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