Manu Abraham wrote: > On Wed, Mar 2, 2011 at 6:35 PM, Olin Lathrop > wrote: >> Manu Abraham wrote: >>> My question is: >>> How can I pullup RA0 while TRISA is configured as HiZ mode (input, >>> TRISA.0 =3D 1) ? >> >> With a pullup resistor. Resistor goes between RA0 and Vdd. > > > Yeah, that's what I wondered. I already do have a 4k7 resistor from DQ > to Vdd as described in the DS1820 datasheet. But the whole confusion > that dawned upon me is from the flow chart where it mentions "Master > Enables Strong pullup". Since it is already pulled up by a resistor, > why mention that it in a software flowchart ? Argh! I just sent you a reply and now see that I replied to a CC you sent me and it therefore didn't go to the list. There is nothing in it for me t= o send you a personal reply. STOP SENDING ME PRIVATE MESSAGES. ******************************************************************** Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products (978) 742-9014. Gold level PIC consultants since 2000. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .