Hi, another Peter, I don't have any detailled information except "doesn't work". My sales people ususally help the customers by resetting to mode 1 (doing those spefific key press sequences, this toggles between mode1 and mode2 and can be repeated until eeprom fails), so I don't have a single device with this fault condition here on my desk. Hope somebody will send me one for further examination. The info about "winter time failure" is interesting, here we have winter time momentarily... Will let you know as soon as I have more details. Thanks for you comments! Peter Bob Axtell cotse.net> writes:=20 > I spend several weeks on this, finally pinning the problem on our=20 > Blessed Microchip (sigh). .... snip > This method, that I call "Best of 5", always works for me. >=20 > Otherwise, drop the internal PIC EEPROM and use an external EEPROM,=20 > which does not have super small cells. Bob, thanks for sharing that. This is majority voting essentially, no?. Have you considered using 2 of 3 voting instead? Have you seen any patterns in the faults that were fixed? I mean set up some kind of logging method so you could analyze faults later? Do faults affect adjacent cells in the sens= e of cache line or block adjacent or simply adjacent as in consecutive addresses? Also did you try to spread the joined cell groups of 5, so cells in a group were not adjacent or did you leave them adjacent? If you did, did it make any difference? External EEPROMs also fail in long term use, frequently as a side effect of ESD elsewhere in the circuit. Also many EEPROMs of 'new' vintage which are very cheap have also undergone die shrinks. I do not know how to tell them apart, I think that the only way is to measure actual writ= e time required or power consumption under the same circumstances, lower time or current drain may indicate a die shrink. To the O.P.: Peter, did you see a pattern in the failed devices? Like datecodes, or use in a certain electrical environment (f.ex. in combination with other equipment which can cause RFI or pulse injection)= , or use in high heat/humidity? Perhaps use in some new environment like RF toll gates, or back-scattering X-ray portals used at border crossings or such? I once saw an interesting pattern of ESD related failures in a product (not mine) which occurred in the dead of Winter. The pro- duct was a consumer product and used indoors. CMOS devices were damaged and sometimes microprocessors zapped. We searched a lot at the time, as a service provider, for a fault. The only thing we could correlate with, and that was years later, was humidity. Winter caused humidity under 30% when the bulk of the faults occurred. This causes much stronger static discharges as higher voltages can build up and not bleed down naturally. The manu- facturer discontinued that product but we could later see that the ESD prevention measures at board edges and in other areas that mattered were much better done in later products, which also did not fail in that way anymore. The entry point for ESD may have bee= n an unshielded modular IR receiver near the board edge and near some user accessible keys. All later models used shielded IR receiver modules. -- Peter (another) -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membershi= p options at http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .