Immediate goal is minimal working sine wave synthesis example with the=20
33F audio DAC for my own edification.  Once it works I'll be happy to=20
put it in an enclosure with an LCD, a potentiometer, and a buffer amp to=20
serve as an audio function generator.

I would agree with you re: overflow, but I sat and single stepped=20
through a couple of cycles (hundreds of steps), watching the phase=20
accumulator. It wrapped properly, and the table entries appear to be=20
valid.  Unless something different is happening at normal speed. =20
(Normally I would use a table length of a power-of-two but I wanted to=20
reply to IVP in the terms he used (one entry per degree).)

My second thought was that somehow the interrupt was being retriggered=20
too early, either incrementing the phase accumulator too many times or=20
overflowing the FIFO.  So I added an explicit test for FIFO full=20
condition, to no avail.

My third thought was WDT, but it's configured off, and now explicitly=20
set off in software, and now I've added ClrWdt() in the main loop "just=20
to make sure".... Behavior doesn't change.

I am now going to double-check my soundcard scope against a 60hz=20
mains-derived signal to eliminate the possibility that it's dropping=20
samples.


Joe




On 2011-02-08 15:29, Olin Lathrop wrote:
> Joe Koberg wrote:
>> http://s3.ae5ne.com.s3.amazonaws.com/dspic33_bad_sinewave.pdf
> I have no idea what you're trying to do and what this waveform is suppose=
d
> to look like.  However, this looks very much like high bits wrapping
> somewhere.  That could be due to overflow or improper handling of signed
> versus unsigned integers, for example.
>
>
> ********************************************************************
> Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
> (978) 742-9014.  Gold level PIC consultants since 2000.
--=20
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