On 06/02/11 00:16, Oli Glaser wrote:
> Interesting, I have not used Xilinx FPGAs - you mean the e.g. Spartan
> series have no LVDS capable models?

Oh no -- the Spartan3 can do LVDS (in fact it has built in LVDS line=20
transceivers and terminators!), as can the Altera Cyclone II and III.=20
The problem is, you don't get many diff-pairs on a chip.

> With Actel (now Microsemi) the ProASIC3 250K gate which I'm currently
> using is ~=A310 and has LVDS/LVPECL available.

I spotted those on Mouser's site this evening -- they look like they=20
could be fun to play with. SRP of $50 for the programmer pod too, which=20
isn't too bad.

> Surely there are some cheap(ish) offerings from Altera or Lattice also -
> need to check all this myself as I would like to have more options FPGA
> wise, looked at/thinking of grabbing one of the "universal" programmers
> e.g. Amontec JTAGkey (I think that's the name, been a while since I
> looked, anyway something along those lines that avoids buying each
> separate programmer - that one does various ARM MCUs too IIRC)

If you want to use the manufacturer's debugging tools (Chipscope,=20
SignalTAP, etc.) then you need the manufacturer-specific programming=20
pods. Altera pods are fiercely expensive, but have been=20
reverse-engineered to the point where they work in UrJTAG and you can=20
build a clone for about 25% of the RRP of Altera's pod. It's basically=20
an FT245R tied to an Altera (or Xilinx, if you prefer) CPLD, which is=20
then tied to a level-translator (optional, only needed if you want to=20
use 2.5V or 1.8V parts).

I built a neat little hacked-together USB Blaster clone for about =A335=20
(PCB was home-etched), and it'll go down to about 1.5V. To program the=20
CPLD, I fished a Xilinx Parallel Cable III out of the spares bin, added=20
some greenwires and an IDC header, and used UrJTAG to flash the Altera=20
CPLD. Worked great.

--=20
Phil.
piclist@philpem.me.uk
http://www.philpem.me.uk/

--=20
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