Going 3.3 -> 5V and just for fun

Q1 =3D NPN "Logic transistor" with internal base resistor.
5V in enable pullup (or use an R)

V_3V3_Out - Q1e
3V3+ - Q1b
Q1c - V5_in

Single eg SOT23 or smaller per channel.

_________

Bidirectional MAYBE MOSFET version.

MOSFET as above.
No rg needed but Vth < 3V.

For 3V -> 5V works as above.

Now make 3V =3D input, 5V =3D output, same connection as before.
Input internal pullup or R.

V5_out high - Vin_3V floats pulled high, all well.
V5_out low -> pulls V3In low via FET body diode.
FET is turned on a Vg > Vs but as Vd < Vg all is well.

Getting speed may be "problematical".
Sure to be bugs.
Pullups annoying.
Looks like fun.


R
--=20
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