Quoting Olin Lathrop <olin_piclist@embedinc.com>:

> PICdude wrote:
>> The SCL line went to logic high or low (never floating).
>
> That's a bad idea in general.  You can get away with it if you're not usi=
ng
> multi-master and you're really sure none of the slave devices on the bus =
do
> clock stretching.

Correct.


> You can still do it right easily enough with bit banging (in fact I usual=
ly
> do, due to so many problems with the MSSP in IIC mode), just bang the TRI=
S
> bit while keeping the port bit 0, and of course add a pullup.  You can us=
e a
> pin with a internal pullup if you slow the clock enough to compensate for
> the slow rise times.

That's what's I was doing on the SDA line, but had no need for it on =20
the SCL line.  Will be doing this for a newer use, where I'll be =20
running I2C faster, and clock-stretching will be possible.

Cheers,
-Neil.



--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.