> We're designing a boost converter and are discussing where we should
> trigger the adc to sample during the pwm period.  I'm thinking that
> because we have a maximum duty cycle of 85% we should fix the sample
> point at the 90% mark so it's always past any tran

"Past" is good. But understanding what "past" really means is a good idea.

Wandering around the edges.
This is aimed at raising more questions and uncertainties and less at
providing instant answers.
Any well founded confusion it creates is a good thing.
Any ill founded confusion should be ignored :-).

You need to be able to take each point or thought below and either know you
have allowed for it OR have determined that it is irrelevant or that I am
talking rubbish (as least as far as your system goes).

Olin's answer seemed to be based on the assumption that the ADC's role was
voltage loop control of the boost converter - which is probably correct.

Do you also have cycle by cycle current loop control? - if so this is
arguably (and usually) your primary cycle by cycle control loop with voltag=
e
loop control following along in the background. If so then average is
probably good enough and best as you ultimately want to control voltage to
be what you want the load to see - and it sees some sort of average.
Hopefully your long term mean and your RMS and even your peak are close
enough to each other that it's "almost" irrelevant which was used.

Long on times and short off times (85% duty cycle) indicates an output
voltage substantially higher than input. As Olin says, current transients
will probably be more transient around the switching spike BUT input curren=
t
levels will be higher during the low voltage-higher current input cycle. If
your measurement point fluctuates in voltage with input current variation
(as it may depending on design) and/or on instantaneous output voltage (as
it also may) then best when to sample  depends on which of these effects ca=
n
be most easily minimised, assuming that you don't want them to be allowed
for.

As Olin noted (I think) the variation of the voltage at the sampling point
as seen by the ADC and the actual voltage variations at the ppnt are
separated by filtering, and you may be able to minimise variations in what
you see quite independent of what is actually there. As Olin said, if you
filter too heavily your control loop may suffer (the more so if this is you=
r
sole control loop).

The "true" voltage output is arguably N x the voltage across the lower
element  of the voltage divider N:1 divider  used to sample the output. ie
- It is NOT the voltage across the whole divider as transients are almost
always decouples directly from the top of the divider to the tap so are
magnified in apparent effect by N.
- It is not (perhaps) the voltage that the ADC sees if its ground reference
point is not tied electrically to the bottom of this divider (due to eg
voltage differentials from input current or output voltage levels*).

ie (again) what your ADC "sees" depends on how it deals with the current an=
d
voltage transients on the PCB. By designing and understanding the potential
error signals, current flows, output and input current loops etc you can ge=
t
substantially improved results at possibly zero cost (or bad results also a=
t
no implementation cost). Drawing expected physical current flows on a
physical layout diagram can produce aha moments. Where electrically  is top
and bottom of switch, load, inductor, ADC ground, other grounds wrt error
voltages in the PCB assembly?. Lots of web material available on getting
this correct.

If you do have cycle by cycle current loop control (which usually makes lif=
e
easier overall) note that for duty cycles > 50% your system may be
unconditionally unstable (in theory and in practice) - cured by adding a
clock ramp component or functional facsimile into the error signal.  Very
well covered in the literature. Applicability to your system may require
invocation of Murphy (but usually not Godwin).


Usually much easier than all this sounds. Sometimes not.


  Russell McMahon
--=20
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