Andy Tuthill wrote:
> We're designing a boost converter and are discussing where we should
> trigger the adc to sample during the pwm period.  I'm thinking that
> because we have a maximum duty cycle of 85% we should fix the sample
> point at the 90% mark so it's always past any tran

That's close to the worst thing to do.  The largest transient will be at th=
e
end of the switch pulse, not during it or at its start.

However, if you've got the inductor switching transient coupling into the
A/D signal significantly, then you should fix your grounding and strategy
for containing the switching loop currents first.

Otherwise, when exactly you sample the output voltage depends on what you
are trying to do.  Are you trying to regulate the low points, the high
points, the average, something else?  The easiest is to deal with the
average and know that the ripple doesn't exceed a certain level.  A little
low pass filtering in front of the A/D will help, but not so much that your
control loop becomes unstable.  That of course depends on how often you
apply the control, and what its time constant is.

It also matters where in the cycle you do the computation to determine the
next pulse size.  That has to lag at least one pulse, usually two, with the
full feedback look being sortof a pipeline three pulses long.  With proper
noise control and a little low pass filtering, you can sample based on when
you need the sample and forget about everything else.


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