On 04/01/11 03:25, Marcel Duchamp wrote:
> Divide and conquer.  Perhaps the VCO can't slew fast enough for the data
> rate?  PLL's have lots of parameters and each must be right (obviously).
>    Go down the list and you will find the problem somewhere probably.

I've pretty much written off the VCXO/74LS "hybrid" design. It's not=20
stable, and I fed the VCXO a several-dozen kHz signal only to see it=20
fall to pieces... Nope, not gonna work.

V2.0 is a total redesign using a "digital PLL" of sorts. I have:
   - A DCM to convert the 13.875MHz input clock (2*Fdat) into a much=20
faster 111MHz clock (16*Fdat). This should provide a reasonable amount=20
of phase resolution :)
   - A transition detector picks out the transitions in the incoming=20
data stream -- the bit clock, with the odd missing clock (or 14 in the=20
case of a Clock Cracker stream).
   - A counter which spends most of its life incrementing at 16*Fdat. If=20
a transition is detected (or the counter value reaches 15), it gets=20
reset to 0. A 'sample trigger' pulse is output when the counter value is=20
equal to 7.

Fdat is the data rate, 6.9375MHz.

The transition detector is a 2-bit shift register which stores the last=20
two samples of the data input. A new sample is clocked in at 16*Fdat:
   shiftreg[1] <=3D shiftreg[0]
   shiftreg[0] <=3D data_in
If (shiftreg[0] =3D=3D shiftreg[1]) and (shiftreg[0] !=3D data_in), then a=
=20
transition occurred and the TRANSITION_DETECTED register is set.=20
Otherwise, TRANSITION_DETECTED is clear.

The counter "is what it is" -- a 5-bit binary counter with asynchronous=20
reset. Think of a 74HC4040, but smaller, and with a pair of fixed-value=20
binary comparators on the output.

It works pretty well -- I rigged the scope to trigger off of=20
SAMPLE_PULSE, set DATA to show full-screen with infinite persistence,=20
and left it running while I made (and drank) a cup of tea. When I came=20
back, there wasn't a single data transition the PLL had missed -- the=20
sample pulse struck right between the samples, plus/minus about 20ns.=20
Close enough to consider "perfect".

Next step: make it work on a Xilinx 9572XL CPLD. 72 macrocells and 34=20
user I/Os... I wonder if I can fit a small FIFO in there too... hmm...

--=20
Phil.
piclist@philpem.me.uk
http://www.philpem.me.uk/
--=20
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