To complement my procrastination here is a simulated implementation (known =
to
work pretty well), which I just uploaded:

   http://ompldr.org/vNnI4eA

The delays are implemented using D flipflops and a fast clock source, they =
can
be replaced with a RC lowpass each. The circuit is implemented entirely usi=
ng
one 74xx00 chip (4 NANDs) but it requires an input buffer if using a RC low=
pass
when the signal source is not another ordinary gate. The RC time-constant c=
an be
increased safely until the output pulse is half as wide as the narrowest in=
put
pulse. Note that the 1st gate is used as an inverter. Another inverter can =
be
pressed into service, from another package on the board, if available.

-- Peter


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