Olin Lathrop wrote: > Nathan House wrote: > =20 >> Schematic: >> http://www.roboticsguy.com/images/misc/pic18f4550_tqfn_schematic.png >> =20 > > You've got to be kidding! You are always judged by the examples of your > work you let others see. The fact that you're not sufficiently embarasse= d > by this says a lot about what kind of engineer you are (or aren't in this > case), even more than the mess itself. > > Schematics are not only to define what's connected to what inside the ECA= D > software, but also to explain the circuit to humans. > > 1 - The pins of IC1 are in pin number order! That may save you a few > minutes making the symbol once, but wastes many times that over the life = of > the schematic as people have to figure out what's where. > =20 meh the pic mostly has logically grouped stuff next to each other anyway=20 so IMO the troubleshooting advantages of keeping the physical layout=20 outweigh any gains that would come from using another layout in the case=20 of pics. > 2 - Do you really need all those big fat circles with Xs thru them to sho= w > no connections (if that's what they indeed are)? Just don't connect > anything to a pin and it will be obvious nothing is connected to it. > =20 From looking at his layout it seems like those represent loose pads=20 connected to the unused IO (not a bad idea if you are trying to make a=20 board flexible, much easier to solder to a pad than straight to the pin=20 of a tiny SMT chip). > 3 - It's nice to have logical flow of signals from left to right. That's > not always possible, especially with complicated ICs, but at least you ca= n > put power on top and ground on bottom. You've got Vdd going every which = way > except the one logical direction, which is up. If you'd bothered arrangi= ng > power going from top to bottom, you might have noticed that D1 is backwar= ds. > See how taking a little care actually makes a concrete difference? > =20 I'd agree on the power, for the signals pretty much every group of=20 signals on that board is bidirectional anyway. > 4 - Neatness counts, since it effects readability. It's even more import= ant > when you expect others to see your work. Since this is of course obvious= , > it logically follows that not taking some care is either stupid or > deliberately rude. So which is it? > > The vertical text and even text overlapping other parts is really sloppy = and > annoying to read. What's with the long label for J1? I don't wee what i= t's > trying to tell us beyond that it's a RJ11 connector. Meanwhile the label > collides with R1. Now how come you couldn't see this for yourself!? > =20 Do you really need to take such an accusatory tone when pointing such=20 things out? > 5 - What's with all the polarized capacitors? Clearly C4 and C5 at 22pF = are > going to be ceramic, which is not polarized.=20 Agreed > None of the other values are > large enough at high enough voltage to require polarized capacitor > technologies. These should all be the much cheaper and more effective > ceramics. > =20 Agreed, provided you are buying from a supplier that stocks them and you=20 are prepared to deal with SMT the modern large capacitance ceramics free=20 you from the pain of polarised capacitors for many applications. Do watch the dielectrics though. Y5V ceramics in particular are nasty=20 with capacitance dropping off heavilly with voltage and temperature, I=20 would avoid them. IIRC X5R, X7R and NPO are the good ceramics. > 6 - If I remember right, 20MHz crystal doesn't work with USB. Did you re= ad > the datasheet before designing the circuit? I didn't think so. Go read = it. > =20 As ususal you are being unessacerally accusatory. Even after reading the=20 datasheet it is very easy to miss something. In this case though the=20 icing on the cake is you've taken the accusatory tone without checking=20 your facts first. 20 MHz is not only fine for USB it's what microchip=20 use on their own demo board. > 7 - 330nF may be in spec for the Vusb cap, but it's definitely on the low > end. Here's a case where the datasheet is misleading and actually > contradicts itself. I've had private communication with Microchip about > this, and you can use considerably more, like 1uF or even higher. > =20 Never had a problem with 220nf on there myself but I have seen reports=20 that bigger is better. > 8 - Where is the power coming from? It says "Power Jack" in the bottom > right corner, but there is no jack there nor anywhere else on the schemat= ic > I can find. > =20 Looks like there are two pads LSP1 an LSP2 in that part of the schematic=20 which i'd assume are the power input > 9 - What's the point of this PIC if it's not connected to anything other > than the USB? As far as I can see, the only connections to other pins ar= e > to the infrastructure around the PIC. Shouldn't there be sensors, > transducers, a serial port, analog inputs, digital outputs, *something*? > > =20 >> Layout: http://www.roboticsguy.com/images/misc/pic18f4550_tqfn_pcb.png >> =20 > > 10 - Do I see this right? You are using a QFN package for the PIC but th= e > other parts around it are all thru hole!!? If that's true, it's really > funny! > =20 I've done similar before. I find SMT passives a PITA to deal with=20 compared to through hole ones so if there is room I see no reason not to=20 use them and given the small number of them in this circuit they don't=20 really take up much room. If you are going to stencil and oven the whole=20 board this doesn't apply but I doubt this is the case here. > 11 - It makes sense for external connectors to be thru hole for mechanica= l > strength, but it looks like the pads on the USB connector short to each > other. This looks to be done with Eagle. Didn't you run a DRC check? > =20 Agreed, always remember to run a DRC (and configure your design rules=20 appropriately for your design and manufacturing process) > 12 - It looks like there is silkscreen writing over pads in a number of > places. Board houses will generally clip silkscreen to the solder mask > layer, but its very sloppy to rely on this. It might hold up the board t= oo. > =20 Agreed > 13 - Daisy chained ground is a really bad idea. At least the local groun= d > around the PIC should be locally connected. The PIC ground over by the > crystal loops halfway around the board before connecting to the other sid= e > of the PIC. Making a single ground plane and blindly connecting all grou= nds > to it isn't the best, but it would be better than what you did. It appea= rs > everything is on one layer. Why not use the bottom at least for ground? > =20 Maybe he wants to make/have it made single sided (btw to the OP: if you=20 are going to get the board made single sided remember SMT parts need to=20 be on the same side as the tracks and through hole parts on the opposite=20 side from the tracks!) But even then there isn't anything obstructing him from just taking all=20 the grounds together to one big pour under the pic --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .