On 24/11/2010 23:01, Philip Pemberton wrote:
> On 24/11/10 22:23, Oli Glaser wrote:
>> Right I see - I assumed there was some reason for it. I take it the FPGA
>> you are using only has one PLL so you can't just try another one.
> The FPGAs have two triple-output PLLs. The catch is that Quartus does
> the allocation "automagically" -- I haven't found a way to tell it "I
> want MASTER_CLOCK_GEN in PLL1, and DATA_SYNCHRONISER in PLL2". That's
> probably because I haven't really done much beyond pin assignments,
> timing constraints and synchronous Verilog HDL logic design.

Not used Quartus, so I don't know there, sure the required info will be=20
hidden somewhere in a lengthy datasheet though... :-)
With Libero (Actel's IDE) you can set the PLLs in the "Designer"=20
graphically, or in HDL with various macros (IIRC)
I'm thinking of grabbing some Altera FPGAs shortly, to give them a try.=20
Not sure what will happen with Actel now Microsemi have acquired them.

>   >  Also, are you running it too fast (or close to) - have you tried it =
at
>> different (slower) speeds?  I just find it a little hard to believe the
>> PLL has gone in both FPGAs, though a simple test configuration flashing
>> an LED not working would suggest there is some issue.
> Turned out there was bad soldering on the PLL_VCC(DIGI) and PLL_VCC(ANA)
> pins. Something like 1k5 on one and 10k on the other. Pushing the pin
> with my DMM made the resistance change...
>
> Problem with SAC (lead-free, 96% Sn, with Ag and Cu to make up the
> balance) is that it's damn close to impossible to spot a bad joint by
> appearance alone... unlike SnPb. Damned Eurocrats and their RoHS and WEEE=
 :(
>
> (Yes, I do have two separate production lines: SnPb for my own kit,
> SAC96 for the stuff I make and sell)
>

Ah there you go - it's always the simplest things... :-)
Beats the PLL or PIC not working though, no faulty components to change=20
- hopefully the boards will work okay now..

>> Looks like a very nicely done project by the way - I'm thinking I may
>> use the PMP in the next revision of my board here (using a 250K ProASIC3
>> and 18F24J50) instead of the current serial link between FPGA and PIC
>> (not enough pins available with current configuration)
> Feel free to take any code that helps you -- it'd be cool to see what
> you come up with. I'd appreciate a note in your README, instruction
> manual or whatever, and maybe a photo of whatever you come up with. It's
> always cool to see other people's projects. "Hardware porn" :)
>
> I ran the figures and came up with a theoretical peak transfer rate of
> 12MB/sec using the PMP in unaddressed 8-bit mode, if the data is thrown
> into the bit bucket. If you multiplex the address onto the data bus like
> I have, you'll get no more than 6MB/sec peak. Actual data rates are --
> in my experience -- closer to 1-2MB/sec including data storage (you can
> probably do better in raw ASM, this is in C18). Not bad for a little
> micro with a 1-instruction-per-4-clocks ratio.
>

Thanks, I may do if/when I get round to it - if I use anything I'll=20
certainly let you know.


> I'm toying with the idea of doing a pure-FPGA design based around the
> DiscFerret, which emulates an IDE hard drive. My HP16500B analyser's HDD
> is squealing like it's in serious pain, and finding a suitable CF card
> is likely to be close to impossible. I've been wanting to see what the
> LatticeMico32 core can do for quite some time... :)
>
> Thanks to the DiscFerret, I have about 70% of the parts I need sitting
> in my spares box...
>


--=20
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