On 24/11/10 22:23, Oli Glaser wrote:
> Right I see - I assumed there was some reason for it. I take it the FPGA
> you are using only has one PLL so you can't just try another one.

The FPGAs have two triple-output PLLs. The catch is that Quartus does=20
the allocation "automagically" -- I haven't found a way to tell it "I=20
want MASTER_CLOCK_GEN in PLL1, and DATA_SYNCHRONISER in PLL2". That's=20
probably because I haven't really done much beyond pin assignments,=20
timing constraints and synchronous Verilog HDL logic design.

 > Also, are you running it too fast (or close to) - have you tried it at
> different (slower) speeds?  I just find it a little hard to believe the
> PLL has gone in both FPGAs, though a simple test configuration flashing
> an LED not working would suggest there is some issue.

Turned out there was bad soldering on the PLL_VCC(DIGI) and PLL_VCC(ANA)=20
pins. Something like 1k5 on one and 10k on the other. Pushing the pin=20
with my DMM made the resistance change...

Problem with SAC (lead-free, 96% Sn, with Ag and Cu to make up the=20
balance) is that it's damn close to impossible to spot a bad joint by=20
appearance alone... unlike SnPb. Damned Eurocrats and their RoHS and WEEE :=
(

(Yes, I do have two separate production lines: SnPb for my own kit,=20
SAC96 for the stuff I make and sell)

> Looks like a very nicely done project by the way - I'm thinking I may
> use the PMP in the next revision of my board here (using a 250K ProASIC3
> and 18F24J50) instead of the current serial link between FPGA and PIC
> (not enough pins available with current configuration)

Feel free to take any code that helps you -- it'd be cool to see what=20
you come up with. I'd appreciate a note in your README, instruction=20
manual or whatever, and maybe a photo of whatever you come up with. It's=20
always cool to see other people's projects. "Hardware porn" :)

I ran the figures and came up with a theoretical peak transfer rate of=20
12MB/sec using the PMP in unaddressed 8-bit mode, if the data is thrown=20
into the bit bucket. If you multiplex the address onto the data bus like=20
I have, you'll get no more than 6MB/sec peak. Actual data rates are --=20
in my experience -- closer to 1-2MB/sec including data storage (you can=20
probably do better in raw ASM, this is in C18). Not bad for a little=20
micro with a 1-instruction-per-4-clocks ratio.

I'm toying with the idea of doing a pure-FPGA design based around the=20
DiscFerret, which emulates an IDE hard drive. My HP16500B analyser's HDD=20
is squealing like it's in serious pain, and finding a suitable CF card=20
is likely to be close to impossible. I've been wanting to see what the=20
LatticeMico32 core can do for quite some time... :)

Thanks to the DiscFerret, I have about 70% of the parts I need sitting=20
in my spares box...

--=20
Phil.
piclist@philpem.me.uk
http://www.philpem.me.uk/
--=20
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