On 24/11/2010 18:44, Philip Pemberton wrote:
> On 24/11/10 17:50, Oli Glaser wrote:
>> I am probably missing something here, but I'm wondering why you couldn't
>> have discovered this by checking the PMP lines with a scope or analyser
>> - I assumed you had done something like this to narrow it down to
>> (looking like) the PIC being the problem (i.e whether the data is
>> actually arriving)
> I forgot that I'd rewritten the PMP logic -- it originally used PMRD and
> PMWR directly as clocks, which caused some metastability issues. I
> rewrote it to use the master PLL clock, which fixed the metastability
> but now means that no clock =3D=3D no FPGA activity.
>
> Also, I can't get SMD probes onto the pins: they're too close together.
>

Right I see - I assumed there was some reason for it. I take it the FPGA=20
you are using only has one PLL so you can't just try another one. Also,=20
are you running it too fast (or close to) - have you tried it at=20
different (slower) speeds?  I just find it a little hard to believe the=20
PLL has gone in both FPGAs, though a simple test configuration flashing=20
an LED not working would suggest there is some issue.
Looks like a very nicely done project by the way - I'm thinking I may=20
use the PMP in the next revision of my board here (using a 250K ProASIC3=20
and 18F24J50) instead of the current serial link between FPGA and PIC=20
(not enough pins available with current configuration)

--=20
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