On 24/11/10 17:50, Oli Glaser wrote:
> I am probably missing something here, but I'm wondering why you couldn't
> have discovered this by checking the PMP lines with a scope or analyser
> - I assumed you had done something like this to narrow it down to
> (looking like) the PIC being the problem (i.e whether the data is
> actually arriving)

I forgot that I'd rewritten the PMP logic -- it originally used PMRD and=20
PMWR directly as clocks, which caused some metastability issues. I=20
rewrote it to use the master PLL clock, which fixed the metastability=20
but now means that no clock =3D=3D no FPGA activity.

Also, I can't get SMD probes onto the pins: they're too close together.

--=20
Phil.
piclist@philpem.me.uk
http://www.philpem.me.uk/
--=20
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