On 23/11/10 20:36, Barry Gershenfeld wrote:
> I can think of an uninitialized variable or config register that often co=
mes
> up "lucky".  Or a line that shouldn't be floating but is mostly managing =
to
> be in the right state just from stray capacitance.  I'd say, though, from
> looking at the thoroughness of your work, that none of this is likely.  B=
ut
> you asked for w.a.g's.

I'm initialising all the PMD registers on startup..

... And I've just flashed a test program into the FPGA, which blinks the=20
LED using the PLL. No clock out from the PLL. Interesting... The FPGA=20
side of the Parallel Master Port is run from a PLL-derived clock, so if=20
the PLL is shagged, then that would explain why my PIC can't talk to the=20
FPGA.

I've tweaked the logic so that it jams the FPGA Status LED on if the PLL=20
fails to lock. That should make this sort of thing "a little" easier to=20
spot in future...

> Incidentally, that is a very cool project.  I have been dreaming of /
> wishing for such a thing for a very long time.  The FPGA is good evidence=
 of
> why we've had to wait so long.  Or of how far I would have gotten had I
> tried it.
>
> Your FAQ maybe should mention if you've ever considered making the hardwa=
re
> available.

The hardware is available -- or will be once I've figured out why I'm=20
getting so many failures. The FPGAs are old parts though (on the shelf=20
for a couple of years) so I guess some issues are inevitable.

I've updated the FAQ with ordering details.

Thanks,
--=20
Phil.
piclist@philpem.me.uk
http://www.philpem.me.uk/
--=20
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