On 23/11/10 11:03, alan.b.pearce@stfc.ac.uk wrote:
>> My ATE tests run a bunch of tests on the FPGA-to-PIC comms link:
>>     1) PIC =3D>  FPGA Comms
>>        The PIC uses two I/O pins (RE0 and RE1) to communicate with a
> small
>>        shift register / FSM on the FPGA. This FSM latches the state of
> the
>>        other ten FPGA I/Os, then feeds this data back to the PIC over a
>>        two-wire "SPI-like" link. The PIC reads 23 bits: 20 zeroes, a
> one,
>>        then the 10 data bits.
>
> Hang on, is that 23 bits, 31 bits, or 54 bits? ... Probably doesn't
> matter as you say it passes this test.

I fail at math.... 31 is the correct total. In order:
   20 zeroes
   1  one
   10 data bits
   Repeat ad nauseum

> Are you sure it is the PMP, and not the FPGA that is the problem?

If I make my code fall back to bitbanging the PMP, it works fine. Except=20
it knocks a nice big chunk off the achievable data rate :(

> As the code in all the PICs is the same, can you swap them between PCBs?
> I am guessing they are soldered in, but it would seem to me to be worth
> swapping one pair between a working and a non-working pair of PCBs.

I'd rather not swap the PICs around -- of the three working boards, only=20
one is lead-free. Mixing SnPb and SnAgCu lead-free tends not to go very=20
well.

For bonus points, these boards are from Gold Phoenix -- and I've been=20
having issues with pads lifting during soldering. Pads with tracks=20
attached tend to survive, but the 'loose' ones (pads without connecting=20
tracks) don't.

I have a fresh tube of 25 PICs due in from DigiKey tomorrow morning,=20
along with some more FPGAs, so I can swap for one of those. Given that=20
the FPGA loopback tests are going fine, and the past issues I've had=20
with the 18F85J50, I'm inclined to blame the PIC...

--=20
Phil.
piclist@philpem.me.uk
http://www.philpem.me.uk/
--=20
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