> My ATE tests run a bunch of tests on the FPGA-to-PIC comms link:
>    1) PIC =3D> FPGA Comms
>       The PIC uses two I/O pins (RE0 and RE1) to communicate with a
small
>       shift register / FSM on the FPGA. This FSM latches the state of
the
>       other ten FPGA I/Os, then feeds this data back to the PIC over a
>       two-wire "SPI-like" link. The PIC reads 23 bits: 20 zeroes, a
one,
>       then the 10 data bits.

Hang on, is that 23 bits, 31 bits, or 54 bits? ... Probably doesn't
matter as you say it passes this test.

>    3) PMP Data Bus Test
....
> Here's the issue. Tests 1 and 2 pass on all four boards. If I shove a
> piece of wire between a pin and ground, I get a FAIL on whichever test
> is running at the time. This is good...
>=20
>=20
> Problem is, only two of the four boards can actually communicate with
> the FPGA using the PMP. The other two always return a value of 0x00
when
> reading FIXED55 and FIXEDAA.
>=20
>=20
> Can anyone think why the PMP might do this?

Are you sure it is the PMP, and not the FPGA that is the problem?=20

As the code in all the PICs is the same, can you swap them between PCBs?
I am guessing they are soldered in, but it would seem to me to be worth
swapping one pair between a working and a non-working pair of PCBs.
--=20
Scanned by iCritical.

--=20
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