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Hi,
Looking at section 17.4.1.2 of the PIC18F4550 datasheet describes the
contents of the BDSTAT byte of a buffer descriptor.

A couple of paragraphs describe the data toggle synchronization
mechanism (if DTSEN=3D0 the data toggle value is ignored and all packets
are received into RAM and reported to the application; if DTSEN=3D1 the
data toggle is compared to DTS and any packet not matching the
synchronization value is ACKed but not reported to the application).

Another paragraph describes the BDSTALL bit, which causes transactions
associated with that buffer descriptor to return STALL handshakes to
the host.

These paragraphs and the register description tables around them don't
seem to prioritize either of these bits (DTSEN and BDSTALL) over the
other, leading to my question: if DTSEN=3D1 (so toggle checking is
enabled), and DTS=3D0 (meaning I'm expecting a DATA0), and BDSTALL=3D1
(meaning I want to stall further activity), and a DATA1 packet arrives,
which handshake is sent back to the host? Is it STALL (because
BDSTALL=3D1) or is it ACK (because DTSEN=3D1 and there's a sync mismatch)?

Thanks for any clarification,
Chris
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