On 30/10/2010 15:13, Olin Lathrop wrote:
> Pay attention to details.

OK, all of these points are very valid.  However, I do this as a hobby=20
and relying on Eagle for some parts saves a lot of time!  I will take=20
more care to smash the parts and fix labels in future, I tend to spend a=20
lot less time than I should on the schematic.

> Yikes, you've got silkscreen overlapping pads all over the place!

Yes, the silkscreen has issues.  Turns out I exported the tDocu layer=20
along with tPlace.  I will make sure I am more careful when exporting=20
the gerbers for the board house.

(Note that the Eagle USB connector still has silkscreen all over the=20
pads on tPlace, I'll fix that up)

> You apparently didn't use net classes at all, since everything is in the
> default class and its width and other values were never set.

I had not heard of these, so some research is needed for future.  Thanks=20
for the pointer.

> You also clearly didn't run a DRC check, which would have found a number
 > of clearance violations.

Actually the board I uploaded passes the Sparkfun/BatchPCB DRC just fine.

> You do need to get used to making your own parts and definitely
> not rely on the Cadsoft libraries, but you have to learn how to do it rig=
ht
> first.  Several of my libraries are available in my Eagle Tools release a=
t
> http://www.embedinc.com/pic/dload.htm.

I have made a few parts so far but have a lot to learn, clearly.  I have=20
grabbed your tools and will look through the libraries for inspiration.

I am hoping that the new release of Eagle with XML libraries will make a=20
big difference to how easy these things are to share/modify (even just=20
importing a good footprint from one library to another is a pain).

> The bypass cap for IC1 is poorly placed.

Noted.

> As a challenge and to demonstrate some of the things I am talking about, =
I
> edited your board and schematic.  The route was a mess, so I ripped it al=
l
> up.  Somewhere in this process I did something wrong or Eagle got confuse=
d
> about the GND net connections.  Even though I deleted the GND polygon fro=
m
> the top layer, it still thought everything on the GND net was connected a=
nd
> showed no airwires.

That's because GND airwires were hidden (Eagle does show this in the=20
status bar when you run ratsnest).  Didn't you read the manual at all? ;)

> I created a ground polygon on the *bottom* layer, and then rerouted the
> board.  I also replaced your 0805 resistor with my own package since your=
s
> had that bizarre copper ring around them.

The "bizarre copper ring" is not copper, it's on the keepout layer.  It=20
doesn't get used except for a visual guide of where not to place components=
..

The poly on the bottom layer is much better.

 > Note the more readable
> orientation of the text.  I didn't have to do anything special as I have
> separate parts for vertical and horizontal resistors.  I also fixed the t=
ext
> of T1 as a example.

Yes, that is much more readable.

> The oblong holes for the connector pads were just silly.

Very sensible.  I generally use a pin header for insertion into a=20
breadboard, hence the 0.1" spacing.  I'll make some PINHDR variations=20
with round pads.

> I then manually routed all the GND1 SMD pads each with their own via to t=
he
> bottom (ground) polygon.  That leaves as much routing flexibility for the
> remaining signals as possible.  I routed a few obvious connection and pla=
ces
> where I thought the auto router might paint itself into a corner, then au=
to
> routed the rest.

That's a really neat example, thanks.  I have learned a lot creating=20
this and reading through the feedback.

Unfortunately BatchPCB don't allow buried vias and the clearance between=20
some of them is also too small.  A few of the vias could be moved away=20
from pads, I will attempt to do that later.  I might just send off my=20
board and learn from what I get back.  The few I have made before I am=20
slowly documenting on my website.

Thanks so much for taking the time to look at it.

David
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