I just found the answer to my own question - they have a custom ASIC which is a monolithic 40G sample/sec ADC using SiGe (Silicon Germanium) technology. Sean On Fri, Oct 22, 2010 at 6:47 PM, Sean Breheny wrote: > I'll be interested to see what you come up with...Any idea what the > really high-end scopes use? Like the LeCroy Wavemaster 8 (120 G > samples/sec actual). > > Sean > > > On Fri, Oct 22, 2010 at 6:38 PM, Oli Glaser wro= te: >> >> >> -----Original Message----- >> From: Sean Breheny >> Sent: Friday, October 22, 2010 6:04 AM >> To: Microcontroller discussion list - Public. >> Subject: Re: [EE] Clock IC for phase shifting >> >> Well, I have never used it but there is something called a delay >> locked loop (DLL) which is used, I think, to compensate for skew in >> DRAM: >> >> http://en.wikipedia.org/wiki/Delay-locked_loop >> >> You might have a look at that, too. Good luck! >> >> Sean >> >> Thanks, I have never used a DLL either but it's along the right lines, I >> will do some more research. From what I already know they are quite a re= cent >> invention, and I hear Xilinx make good use of them in the Virtex series >> (although they are beyond the budget for this project) >> I may have a look at CPLDs to produce the clocks, as they are more >> deterministic etc - I believe the Rigol 1Gsps xxxxx uses a CPLD (lattice= I >> think) to produce the clocks for 10(!) 100Msps ADCs (actually rated at >> 40Msps so they are overclocking them by over 50%) If they can manage a >> usable result there I'm pretty sure I can come up with something similar= or >> (hopefully) better. >> Anyway, sure I will have fun trying to piece it all together... >> >> >> -- >> http://www.piclist.com PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> > --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .