-----Original Message-----=20
From: Michael Watterson
Sent: Friday, October 22, 2010 8:22 AM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Clock IC for phase shifting

  On 22/10/2010 01:34, Sean Breheny wrote:
> I would have thought that the standard way to do this would be to use
> either a 4x clock and create four phases from it, or a 2x clock and
> use both rising and falling edges to create four phases. This seems
> like a much more solid approach than relying on a delay module with a
> sub-cycle delay.
>
> Sean
Yes.. I thought of that. Easy at 10MHz.
but at 200MHz, you need 800MHz clock. "fun" to make stable and jitter
free, though /4 makes it x4 better. Maybe ECL dividers I don't know. Any
dividers I bought at 400MHz to 3GHz have been 16/17, 32/33, 64/65 etc
prescalers.

Yes, it all gets a lot more tricky at the high speeds, and there is less an=
d=20
less written on these kind of subjects (or it has been but it's not=20
public) - I think I have got a few ideas though. NI do make a dedicated IC=
=20
especially for interleaving clocks and jitter cleaning (I was hoping someon=
e=20
knew of a cheaper alternative), and also produce dual ADCs that have the=20
logic on board to interleave them, trouble is each chip costs about as much=
=20
as the rest of the stuff already on the board, so I can't justify doubling=
=20
the cost just for a clock IC.


--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.