-----Original Message-----=20
From: Sean Breheny
Sent: Friday, October 22, 2010 6:04 AM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Clock IC for phase shifting

Well, I have never used it but there is something called a delay
locked loop (DLL) which is used, I think, to compensate for skew in
DRAM:

http://en.wikipedia.org/wiki/Delay-locked_loop

You might have a look at that, too. Good luck!

Sean

Thanks, I have never used a DLL either but it's along the right lines, I=20
will do some more research. From what I already know they are quite a recen=
t=20
invention, and I hear Xilinx make good use of them in the Virtex series=20
(although they are beyond the budget for this project)
I may have a look at CPLDs to produce the clocks, as they are more=20
deterministic etc - I believe the Rigol 1Gsps xxxxx uses a CPLD (lattice I=
=20
think) to produce the clocks for 10(!) 100Msps ADCs (actually rated at=20
40Msps so they are overclocking them by over 50%) If they can manage a=20
usable result there I'm pretty sure I can come up with something similar or=
=20
(hopefully) better.
Anyway, sure I will have fun trying to piece it all together...


--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.