On 22/10/2010 01:34, Sean Breheny wrote: > I would have thought that the standard way to do this would be to use > either a 4x clock and create four phases from it, or a 2x clock and > use both rising and falling edges to create four phases. This seems > like a much more solid approach than relying on a delay module with a > sub-cycle delay. > > Sean Yes.. I thought of that. Easy at 10MHz. but at 200MHz, you need 800MHz clock. "fun" to make stable and jitter=20 free, though /4 makes it x4 better. Maybe ECL dividers I don't know. Any=20 dividers I bought at 400MHz to 3GHz have been 16/17, 32/33, 64/65 etc=20 prescalers. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .