-----Original Message-----=20
From: Sean Breheny
Sent: Friday, October 22, 2010 1:34 AM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Clock IC for phase shifting

>I would have thought that the standard way to do this would be to use
>either a 4x clock and create four phases from it, or a 2x clock and
>use both rising and falling edges to create four phases. This seems
>like a much more solid approach than relying on a delay module with a
>sub-cycle delay.

Thanks for the reply Sean.
Yes, I considered this first and may do it, but I should have been clearer=
=20
in my first post - the reason I want to control the phase is so I can=20
calibrate the clocks as part of the ADC interleaving to compensate for=20
trace/gate/parasitic delays etc. The higher the speeds the more important=20
this will be I expect.
I'm sure I would probably get pretty close with the above method if I'm=20
careful, but I was hoping there was some dedicated IC that could give me th=
e=20
option of adjusting the clocks if needed. From what I have read in various=
=20
HP, Agilent app notes this is the kind of thing they do when interleaving=20
ADCs as one part of the calibration (others being using DACs to adjust for=
=20
INL and DNL and so on)  - apparently even a couple of picoseconds at high=20
speeds can skew things quite a lot.
I may just use complementary clocks with a programmable delay line - part o=
f=20
this is also just out interest I would like to be able to put the clock out=
=20
purposely and compile some (of my own) data on how it affects things. I may=
=20
remove various test features later on, but it would be good to have as much=
=20
control as possible for this prototype version so I can work out how far I=
=20
can push things.=20


--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.