I would have thought that the standard way to do this would be to use either a 4x clock and create four phases from it, or a 2x clock and use both rising and falling edges to create four phases. This seems like a much more solid approach than relying on a delay module with a sub-cycle delay. Sean On Thu, Oct 21, 2010 at 12:24 PM, Oli Glaser wrot= e: > Hi all, > > I have decided to have a go at Time interleaved clocking for the ADCs in = the > scope I am designing. The current version goes at 200Msps and will probab= ly > stay that way (with maybe equivalent time sampling too, but that's anothe= r > story), but would like to try to go for up to 1Gsps in future versions, o= r I > may adapt the current version to interleave the two ADCs to achieve > 400-500Msps to make the most of the hardware if there is not too much cos= t > added. > I have the theory and a plan pretty well sorted for setup, calibration et= c, > and have started sketching a proto, but am having problems finding a > (reasonably priced) IC that will phase shift the clocks whilst maintainin= g > minimal jitter. Obviously I could use the FPGAs PLL, or delay with a filt= er > etc, but these methods add too much jitter than would be acceptable for > decent SNR, so would rather a dedicated clock generator. > So basically does anyone know of any good ICs to produce say, 2 low jitte= r > (lets say <100ps rms), 200MHz clocks 180 degrees apart? Or up to 4 200MHz= 90 > degrees apart. I will consider anything, but <=A310 would be most prefera= ble > (I found one IC but it was >=A330 and did way more than I needed spec wis= e) as > we are still aiming to keep things cheap. > > > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .