Hi all,

I have decided to have a go at Time interleaved clocking for the ADCs in th=
e=20
scope I am designing. The current version goes at 200Msps and will probably=
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stay that way (with maybe equivalent time sampling too, but that's another=
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story), but would like to try to go for up to 1Gsps in future versions, or =
I=20
may adapt the current version to interleave the two ADCs to achieve=20
400-500Msps to make the most of the hardware if there is not too much cost=
=20
added.
I have the theory and a plan pretty well sorted for setup, calibration etc,=
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and have started sketching a proto, but am having problems finding a=20
(reasonably priced) IC that will phase shift the clocks whilst maintaining=
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minimal jitter. Obviously I could use the FPGAs PLL, or delay with a filter=
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etc, but these methods add too much jitter than would be acceptable for=20
decent SNR, so would rather a dedicated clock generator.
So basically does anyone know of any good ICs to produce say, 2 low jitter=
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(lets say <100ps rms), 200MHz clocks 180 degrees apart? Or up to 4 200MHz 9=
0=20
degrees apart. I will consider anything, but <=A310 would be most preferabl=
e=20
(I found one IC but it was >=A330 and did way more than I needed spec wise)=
 as=20
we are still aiming to keep things cheap.


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