-------------------------------------------------- From: "Philip Pemberton" Sent: Friday, September 24, 2010 4:49 PM To: "Microcontroller discussion list - Public." Subject: Re: [PIC] A catalogue of cock-ups > On 24/09/10 16:35, Michael Watterson wrote: >> Sounds great. I have a Spartan 3E starter kit and was thinking 18F + JAL >> + touch LCD to add a GUI to an SDR on the FPGA might be easier than >> trying to do all in FPGA. > > Probably. I've done LCD framebuffers and SoCs in FPGAs though, it's not > that hard. Timing generation is a snap, and if your LCD wants LVDS you > can either use the FPGA vendor's SERDES core, or bolt on one of NSC or > TI's parallel-to-LVDS (PanelLink) converter chips. > > I've reused old laptop LCDs before today. The hardest part of the > endeavour is usually getting the backlight inverter going (figuring out > the pinout). Dell tend to use custom inverters with I2C bus links, > whereas most of the other manufacturers go with +5V/0V and a 3- or 4-bit > parallel 'brightness' (lamp current) value. > > Go with something you can find a connector for, and you won't have many > problems. Samsung LCDs are a good target, assuming they don't have "DELL > P/N" or "IBM P/N" stamped on them. Email Samsung-SDI and ask for a > datasheet or pinout and they'll usually email it back to you within a > couple of days. They also have a habit of using the JST LVDS connectors, > which are stocked by Farnell and Mouser (and probably DKUS as well). > > In short: "Easy." Interesting - I have a bunch of old laptops, which I was wondering about=20 using the LCDs of for prototyping ideas. Might have a go at using one.. Talking of LVDS to parallel, in my FPGA/18F setup I am interfacing to an AD= C=20 at what will be reasonably high speeds (>100Msps) at the moment it is only = a=20 2 layer prototype (just knocked together to verify the design and logic=20 etc - I used the free "Go Naked" service from Spirit Circuits) the ground i= s=20 not solid, and it was made for easy hand soldering so traces are long etc. I am obviously getting less than optimal results much past 60MHz, although= =20 it's all working "properly" otherwise. The performance should improve=20 considerably with a new board, which will be 6 layer in the next version,=20 but also I am using the standard IOs on the FPGA (ProASIC3 150k gate - no=20 LVDS available) This is fine as the initial goal of >50MHz has been met, bu= t=20 would like to push it faster now. I was thinking I may use the LVDS available on the next version up in the=20 ProASIC3 family (250k) and an interface chip. What would be the plan is to= =20 have the FPGA process the data in parallel at 1/4 the speed (say 40MHz for= =20 32 bits to RAM from the 8-bit ADC running at 160MHz) thus keeping the high= =20 speed parts to a minimum. Do you (or does anyone else) have any recommendations for any decent chips= =20 (I will check out the above, but any advice will help) that will do the job= ?=20 The ADC is a NI ADC08200 200Msps, with standard TTL/CMOS compatible outputs= ..=20 The cheaper the better as I am trying to keep the final price down, but I=20 don't want to compromise on the performance so if necessary will pay=20 whatever if there is nothing "cheap" (say <=A35) available. The other option is to change ADCs to one with LVDS outputs, so any=20 suggestions there would be good too (sorry for the random question, should= =20 have put this all in a new thread really I suppose..) =20 --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .