Philip Pemberton wrote:
> I'm seeing the PK2 pull MCLR low, then raise it for about 520us, then
> low for 1.04ms, then high for the remainder. So MCLR is doing
> *something* at least.

That's a good start.  Now look at PGC and PGD.  Maybe you get lucky and see
one of them stuck high or low.  Look at both of them simultaneously and mak=
e
sure the clock edges look good and that the data line seems to have settled
by the clock edge.  Excessive capacitive loading would make them look
rounded and possibly too slow.


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