I am building a test apparatus (ok, it's a cable mapper) which will=20
require around 256 bits of I/O on a pic system.  Maybe even more.

I'm looking at using some MCP23S17's, driven by a PIC18f46J50.  I want=20
to use the SPI version because I can use the /CS input to select 'banks'=20
of S17's.

The immediate question I had was how many I can drive....  And the=20
datasheets are making me think that the answer might be 'an impossibly=20
large number'.

On the 'J50, Port B/C can drive 25ma, which is where the SPI pins=20
are.    On the 'S17's, the input leakage current is +-1uA.   I can't=20
find any other specs which seem to match... I'm assuming that since this=20
is CMOS, that 1uA is in the realm of what I might expect..   This would=20
indicate that I should be able to drive like 25,000 inputs..

The other direction is lacking in some specs... but even if the specs=20
are way worse, I can still drive many more than I would need.

What I seem to be missing is capacitive loading specs on the inputs. =20
We'll be on a very small board so I don't expect to get much capacitance=20
other than what the SPI inputs might present to the drivers.  I'm=20
hoping/guessing that is will be relatively low in comparison to the=20
drive as well, but I have no way to tell from the datasheet that I can=20
see....

Am I missing something, or is the fanout way larger than I need to even=20
worry about?

-forrest





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