On Sat, 2010-08-28 at 19:12 +0100, Michael Watterson wrote:
> Also of course you can use both in the same project, especially if some=20
> off the shelf core is in the opposite language to the one you are=20
> writing in.

You often can, but I'd STRONGLY recommend not mixing languages,
especially those new to HDL.

While most tools "support" mixed language mode, the most time consuming
tool related problems I've had dealt with the mixing of code. What the
vendors SAY works isn't always what ends up working. As recently as two
weeks ago I hit a bug in the Xilinx toolkit when trying to call verilog
code from a VHDL tb.

If you're using a chunk of IP that is only available in the "other"
language then I suppose you don't have a choice. Personally, I just skip
any IP that isn't of the language I need and either find one that is in
the language I need, or write it myself (sometimes writing IP yourself
takes less time then figuring out how to integrate some IP and debug
it's bugs).

TTYL

--=20
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