On 28/08/2010 17:26, Herbert Graf wrote:
> On Sat, 2010-08-28 at 00:43 +0100, Michael Watterson wrote:
>> On 27/08/2010 19:12, Herbert Graf wrote:
>>> If you know C, then verilog will feel familiar. I'd steer clear of VHDL=
,
>>> it can be very "interesting" in the way it does things, and is more of =
a
>>> hill to climb.
>>>
>>> TTYL
>>>
>> That's exactly why he should learn VHDL and then Verilog. The Familarity
>> of Verilog to a C programmer is a trap.
>> It's not a program in the normal C sense at all. But a way of specifing
>> behaviour of a totally parallel system.
> Very true, but to be frank I find it EASIER to write "horrible" code in
> VHDL then in Verilog, perhaps it's just a personal way of thinking, but
> I just find writing good code easier in Verilog.
>
> That said, VHDL is on the downhill slope, more and more companies are
> switching to exclusively use Verilog (my company completely switched
> over 3 years ago). While a ton of code is out there in VHDL, the newest
> development is all Verilog.
>
> Even today, some code is now being written in system verilog. The
> benefit there is system verilog is a superset of verilog, so learning it
> isn't too bad (although it is VERY different in some ways, my first look
> at system verilog felt like I was living on a different planet).
>
> I stand by my recommendation: bypass VHDL, it's archane in syntax, it's
> being used less and less, and Verilog is easier to learn (for most).
>
> TTYL
>
>
Though VHDL isn't arcane to people with experience of Modula-2 and ADA=20
co-routines and syntax and of experience of Occam.

I think USA and US companies are more Verilog and other folks VHDL. But=20
even if you are going to use Verilog it will help in understanding to do=20
some VHDL tutorials.
Also of course you can use both in the same project, especially if some=20
off the shelf core is in the opposite language to the one you are=20
writing in.


--=20
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