On Sat, 2010-08-28 at 00:43 +0100, Michael Watterson wrote:
> On 27/08/2010 19:12, Herbert Graf wrote:
> >
> > If you know C, then verilog will feel familiar. I'd steer clear of VHDL=
,
> > it can be very "interesting" in the way it does things, and is more of =
a
> > hill to climb.
> >
> > TTYL
> >
> That's exactly why he should learn VHDL and then Verilog. The Familarity=
=20
> of Verilog to a C programmer is a trap.
> It's not a program in the normal C sense at all. But a way of specifing=20
> behaviour of a totally parallel system.

Very true, but to be frank I find it EASIER to write "horrible" code in
VHDL then in Verilog, perhaps it's just a personal way of thinking, but
I just find writing good code easier in Verilog.

That said, VHDL is on the downhill slope, more and more companies are
switching to exclusively use Verilog (my company completely switched
over 3 years ago). While a ton of code is out there in VHDL, the newest
development is all Verilog.

Even today, some code is now being written in system verilog. The
benefit there is system verilog is a superset of verilog, so learning it
isn't too bad (although it is VERY different in some ways, my first look
at system verilog felt like I was living on a different planet).

I stand by my recommendation: bypass VHDL, it's archane in syntax, it's
being used less and less, and Verilog is easier to learn (for most).

TTYL


--=20
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