On 27/08/2010 19:12, Herbert Graf wrote:
>
> If you know C, then verilog will feel familiar. I'd steer clear of VHDL,
> it can be very "interesting" in the way it does things, and is more of a
> hill to climb.
>
> TTYL
>
That's exactly why he should learn VHDL and then Verilog. The Familarity=20
of Verilog to a C programmer is a trap.
It's not a program in the normal C sense at all. But a way of specifing=20
behaviour of a totally parallel system.

--=20
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