It is difficult to give specific advice without seeing the code or
knowing what stage of development your project is at.

Obvious points are :

1. This device supports up to 20Mhz. Do you have pins available to do
this with your hardware setup ?
This would run the code faster and shorten the time in your ISR. Perhaps
not enough to achieve the tolerance you require.

2. Use only essential code in the ISR functions. You may already have
this approach but many people don't. Don't forget that on a chip with a
single ISR, the maximum time to process the interrupt code is the sum of
all of your ISR code. Your fastest interrupt (timer) can be held off by
the time to process all of your various interrupts.

3. Some of the other PIC devices have multiple interrupt levels that are
prioritised. Perhaps one of those may be more suitable.

4. bit of a drastic solution but you could use one pic for signal
generation and another for validation.


Barry.




-----Original Message-----
From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On Behalf
Of Steve Smith
Sent: 25 July 2010 04:11
To: 'Microcontroller discussion list - Public.'
Subject: [PIC] Generating and measureing a waveform



Guys:
I have a conundrum that is proving a little difficult to solve.

I need to generate a waveform and then measure the resultant wave after
its been through the unit its testing. It's a stream of 6 x 1.5mS pulses
with 50Us gaps that repeats every 20mS.

That then feeds a widget that stretches the 50Us gaps to 200Us and adds
a trailing edge 200Us period. And inverts the whole thing. This is the
unit being tested.

Generating the pulse stream is easy. A simple timer loop is called every
20mS from an interrupt driven loop. The capture module is then enabled
before each sequential pulse or gap to measure and compare with a
windowed reference value. The good results stored in a couple of flags
and converted into go / no go lamps after 13 consecutive loops.=20

This shows up the latency in the ISR as the periods get stretched by
differing amounts according to which interrupt was called. There are
three Tmr1 for the 1Us clock for the capture module, Tmr2 for the 20Ms
tick to drive the main calling loop these are both the same length and
then there is the capture module.... That is a lot longer and variable
as the leading and trailing edge take differing times....=20

This is stretching the 50Us periods by as much as 50Us.=20

Does anybody have any suggestions to combat this latency ???

It's a F648A with internal 4mhz Osc

Thanks in advance

Steve


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